1. Field of the Invention
This invention relates to microprocessors and, more particularly, to controlling writes to non-renamed register space within an out-of-order execution microprocessor.
2. Description of the Related Art
Many modern microprocessors are capable of executing instructions is a different order than the issue order. They are typically referred to as out-of-order execution processors. A microprocessors that implements the x86 architecture is one example of an out-of-order execution processor. Out-of-order processors create dependencies associated with the architectural register set. Since instructions will not necessarily execute in the sequential order in which they were written, potential conflicts may result from dependencies between certain reads and writes. For example, a read of a result value stored to a given register may be conflicted if a write occurs to the same register before the read occurs. Such conflicts may cause stalls in the pipeline of the microprocessor.
To overcome these conditions many conventional processors use some form of mapping to map virtual register space to a physical register space. When performed dynamically during execution, this mapping is referred to as register renaming. In a fully renamed register space, there may be a physical register copy associated with each virtual register for every possible outstanding instruction in the pipeline. There are various renaming schemes. Two examples are: explicit renaming and implicit renaming. Each scheme may use one or more pools of physical registers with which to map as well as the associated logic. In either scheme, renaming allows for separation of virtual register space and fewer conflicts during out-of-order execution.
In contrast to the renamed register space is another register space that is sometimes referred to as a non-renamed register space. Writes to registers in such non-renamed register space could conflict with certain reads as described above. To avoid these types of conflicts, in some processors, a write to a particular register such as a segment register, for example, may block writes to every other segment register until the write becomes non-speculative. Although this scheme may prevent conflicts to the register space, processor performance may suffer.
Providing full renaming to some non-renamed register space may not be practical since doing so may require a significant amount of additional hardware.